Silicon infrastructure IP

IP you
license.
Chiplets
you commission.

Pre-verified PCIe Gen 6, CXL 3.2, and NoC IP: licensable standalone today. Or engage SignatureIP to design your full Compute, IO, and Memory Expander silicon to spec, assembled from the same blocks.

Motion 1
License IP
Standalone PCIe Gen 6, CXL 3.2, NoC, SysWare & Peripherals: out of the box, ready to integrate
↗
Motion 2
Design a chiplet
Custom Compute, IO, or Memory Expander built to your spec using pre-verified SigIP blocks
↗
30+
IP blocks available today
3
Chiplet dies, custom to spec
Gen6
PCI-SIG certified
32+
Successful SoC projects
COMPUTERISC-V / CPUPartner corecNoCCHI Rev E.bncNoCIOMMUL3/SLCProxy$DMA · Boot · eFUSE · PVTSPI · I2C · UART · GPIOUCIe D2D→ IO siliconIOPCIe Gen 632 GT/s non-flitATC/ATSDTI ✓CXL 3.2.io .cache .memATC/ATSDTI↑SerDes / PHY (partner)ncNoC fabricSFI · AXI4 · CPI · CHIUCIe← ComputeUCIeTransport→PCIe / CXL → hostMEMORYCXL 3.2 SwitchMulti-port routingP0upP1dnP2dnP3expPCIe Gen 6 fabricMulti-chip root complexCoherentbridgeProtocolxlatncNoC managementSerDes / PHY (partner)UCIe D2D← IO siliconCXL → AI servers · memoryUCIeUCIeCompute siliconIO siliconMemory Expander siliconUCIe / Partner
Certified & connected
PCI-SIG certified (32 GT/s, non-flit mode)
CXL Consortium member
UCIe Consortium
RISC-V International
90+ engineers · 5 countries
Siemens Questa sign-off partner
The connection between both motions
The IP you license standalone is the exact same IP inside every chiplet we design.

Every PCIe Gen 6 Subsystem, CXL 3.2 Subsystem, and NoC block in our standalone catalog is also a building block in every Compute, IO, and Memory Expander silicon engagement. License the IP now. Commission the chiplet when you're ready to scale.

IP differentiation

Microarchitected for PPA.
Not just functional.

Every SignatureIP block is microarchitected from first principles to be modular, reusable, and PPA-optimized: low power, minimum latency and highest throughput, high performance, and optimal area. This is the design philosophy baked into every IP in the catalog and every CSS and IOSS we deliver.

Most IP vendors optimise for correctness. SignatureIP optimises for PPA, making the difference between a chip that tapes out on budget and one that does not.

LP
Low Power
Power domains designed modularly at the microarchitecture level, not added as an afterthought. Active, standby, and retention states built into every IP block. PCIe Gen 6 and CXL 3.2 deliver the lowest-power implementations on the market.
ML
Min Latency · Highest Throughput
NoC topologies generated by iNoCulator™ are latency-optimal and throughput-optimal by construction. The tool explores the design space and selects the configuration that meets your exact latency and throughput targets. No over-provisioning, no wasted silicon.
HP
High Performance
1 GHz operating frequency target on PCIe Gen 6. CHI Rev E.b coherency without latency compromise. Performance targets are first-class constraints in the microarchitecture, not post-synthesis wishlist items.
OA
Optimal Area
Modular, reusable microarchitecture eliminates redundancy across IP instances. ATC, ATS, and DTI shared between PCIe Gen 6 and CXL 3.2 subsystems: one NoC attachment point for two protocols. Every block is rightsized, not overbuilt.
PPA by design
Every SigIP block: cNoC, ncNoC, PCIe Gen 6 Subsystem, CXL 3.2 Subsystem, IOMMU, SLC: is modular, reusable, and PPA-optimized at the microarchitecture level. This applies equally to standalone IP licensing and to every CSS and IOSS chiplet design engagement.
Motion 1: IP licensing

Standalone IP.
Out of the box.

Four categories. 30+ blocks. Pre-verified, documented, and ready to integrate into your SoC today: no design engagement required.

Request any datasheet →
Interface: featured subsystems
Standalone licensable
PCIe Gen 6 Subsystem
Lowest-power Gen 6 on the market · RC/EP dual mode · x1–x16 · 1 GHz · PCI-SIG certified
ControllerATCATSDTISFI · AXI4 · CPI · CHI host IFPower mgmt L0s–L2

ATC, ATS, and DTI are pre-integrated: no separate address translation IP required. The DTI provides a clean, pre-verified boundary to your SoC NoC fabric. Zero additional glue logic.

Explore PCIe Gen 6 Subsystem →
Standalone licensable
CXL 3.2 Subsystem
CXL.io · CXL.cache · CXL.mem · Type 1/2/3 · memory pooling · multi-host coherency
ControllerATCATSDTIBack-invalidationMemory pooling

Shared ATC/ATS/DTI architecture with the PCIe Gen 6 Subsystem: one NoC attachment point handles both PCIe and CXL traffic. CXL Consortium member. CXL 3.2 solution with memory pooling and back-invalidation.

Explore CXL 3.2 Subsystem →
Full portfolio: all four categories
Standalone
Interconnect
Network-on-Chip · tag NoC
  • Coherent NoC: CHI Rev E.b
  • Non-coherent NoC (ncNoC)
  • IOMMU
  • System-level cache (L3 / SLC)
  • Proxy cache
  • CHI-AXI · CHI-CPI · AXI4-SFI bridges
Explore Interconnect →
Standalone
Interface
PCIe · CXL · UCIe · tag IO
  • PCIe Gen 6 Subsystem ↑
  • CXL 3.2 Subsystem ↑
  • UCIe D2D interface (partner) (UCIe D2D)
Explore Interface →
Standalone
SysWare
Integration & management
  • DMA engine new
  • Boot flash controller + DMA new
  • eFUSE interface controller (APB)
  • PVT sensor interface (APB)
  • AXI4-to-APB3 bridge
Request datasheets →
Standalone
SoC Peripherals
Board-level I/O · multi-use
  • Debug interface controller
  • SPI master (×4 CS) · SPI slave
  • I2C master (×4) · I2C slave
  • UART · Watchdog timer
  • GP timers · GPIO controller
Request datasheets →
Motion 2: Chiplet design

Your spec.
Our pre-verified blocks.
One tape-out-ready silicon.

Compute, IO, and Memory Expander silicons are not off-the-shelf products: they're custom design engagements. You bring the architecture requirements. SignatureIP assembles the right pre-verified IP blocks, integrates them to your spec, and delivers a sign-off-ready silicon.

Start a chiplet design conversation →
Silicon 01
Compute
RISC-V / CPU · NoC · cache hierarchy
RISC-V / CPU coresPartner IP
Coherent NoC: CHI Rev E.bSigIP
Non-coherent NoC (ncNoC)SigIP
IOMMU + Proxy cache + SLC/L3SigIP
Protocol bridgesSigIP
DMA · Boot flash · SysWareSigIP
SoC Peripherals (multi-use)SigIP
UCIe D2D interface (partner)Partner
Explore Compute silicon →
Silicon 02
IO
PCIe Gen 6 · CXL 3.2 · D2D hub
PCIe Gen 6 SubsystemSigIP
CXL 3.2 SubsystemSigIP
SerDes / PHY (partner)Partner
Host interfaces: SFI · AXI4 · CPI · CHISigIP
ncNoC local fabricSigIP
UCIe D2D interface (partner) ×2: UCIe D2DPartner
Explore IO silicon →
Silicon 03
Memory Expander
CXL 3.0 · CXL.mem · Memory Expander
CXL 3.0 Type 3 endpoint (CXL.mem)SigIP
PCIe Gen 6 fabric / routingSigIP
Coherent NoC bridgeSigIP
Protocol translation: CHI-CPI · AXI-SFISigIP
ncNoC management / control planeSigIP
UCIe D2D interface (partner)Partner
Explore Memory Expander →
UCIe chip-to-chip
UCIe D2D · partner-integrated on all dies
CXL chip-to-chip
PCIe Gen 6 physical layer · Memory Expander outbound
iNoCulator™: NoC topology explorer
R[0,0]R[0,1]R[0,2]R[1,0]R[1,1]R[1,2]R[2,0]R[2,1]R[2,2]3×3 Mesh1.6 TB/s targetRTL ready
iNoCulator™ design tool

Design your NoC in the browser.

The only cloud-native NoC EDA tool. Set your targets. The tool designs the topology and generates the optimal RTL configuration.

  • ✓
    cNoC and ncNoC topology generation. Configures for single-silicon monolithic SoCs and multi-silicon chiplet packages: the same tool serves both design motions.
  • ✓
    Full sign-off flow. RTL feeds directly into Siemens Questa simulation. SystemC and QEMU flows available for pre-silicon software bring-up.
  • ✓
    Processor-agnostic. Arm CHI, RISC-V, and custom processor interfaces. Validated integrations with leading RISC-V core partners cores.
Try iNoCulator free →