Silicon 01: Compute chiplet

Coherent
compute
fabric.

UCIe D2D, ncNoC, IOMMU, L3/SLC, and the UCIe D2D interface (partner) that binds all three silicon units: the full interconnect and cache subsystem for your AI or RISC-V SoC compute silicon.

Request IP brief →Design NoC with iNoCulator
Low PowerMin Latency · Highest ThroughputHigh PerformanceOptimal AreaModular microarchitecturePPA-optimizedReusable across SoC variants
cNoC: CHI Rev E.bncNoCIOMMUL3 / SLCProxy cacheUCIe D2D (partner)
COMPUTE SILICONRISC-V / CPU CORESPartner IP — leading RISC-V core partnerCOHERENT NoC (cNoC)CHI Rev E.b · Mesh and ring topology · iNoCulator-generated RTLncNoCNon-coherent fabricProtocol bridgesCHI-AXI · AXI2CHI · CHI-CPI · SFIIOMMUSMMUv3L3 / SLC4–32 MB configurableProxy cacheIO coherencyDMA enginemulti-channelBoot flash ctrl+ DMA · secure booteFUSE · PVTAXI4-APB3 · DebugSoC PeripheralsSPI · I2C · UART · GPIO · Watchdog · TimersUCIe D2D interfacePartner-provided · connects to IO siliconSigIP
01 ComputeUCIe D2D02 IOUCIe D2D03 TransportCXL C2CExternal AI / HPC systems
SignatureIP blocks

Every IP block
in the compute silicon.

Six distinct IP blocks from SignatureIP, plus RISC-V / CPU processor cores from ecosystem partners, form the complete Compute chiplet. Designed together, integrated by iNoCulator, signed off with Siemens Questa.

SigIP · Interconnect

Coherent NoC (cNoC)

The central coherent interconnect backbone for CPU/GPU cores, AI accelerators, and HBM controllers. CHI Rev E.b compliant, supporting full cache coherency across all masters.

  • CHI Rev E.b protocol support
  • Mesh and ring topology options
  • Configurable bandwidth, latency, and QoS
  • RTL generated by iNoCulator™
  • Siemens Questa sign-off · SystemC/QEMU flows
  • Arm and RISC-V processor compatible
SigIP · Interconnect

Non-coherent NoC (ncNoC)

Lightweight non-coherent fabric for IO peripherals, DMA engines, and subsystem controllers that don't require full cache coherency; optimized for area and power.

  • Configurable bus widths and topology
  • Low-latency, power-optimized design
  • AXI4 / AXI4-Lite interface compatible
  • Shares iNoCulator toolchain with cNoC
  • Bridges to cNoC via CHI-AXI protocol bridge
SigIP · Sysware

IOMMU

Input/Output Memory Management Unit providing address translation, memory protection, and DMA access control for peripheral devices connected to the NoC fabric.

  • Two-stage address translation (S1 + S2)
  • SMMUv3 architecture compatible
  • TLB and page-table walk hardware
  • Fault reporting to hypervisor / OS
  • Integrated directly into NoC slave ports
SigIP · Sysware

System-level cache (L3 / SLC)

Last-level shared cache providing high bandwidth between CPU clusters, AI accelerators, and main memory. Reduces off-chip traffic and latency across heterogeneous compute tiles.

  • Configurable size: 4 MB to 32 MB+
  • N-WAY set-associative, configurable
  • Stash transactions for prefetch flows
  • Integrated proxy cache for IO coherency
  • CHI compliant; attaches to cNoC HN-F port
SigIP · Sysware

Protocol bridges

The integration glue that connects heterogeneous IP blocks across different bus protocols, enabling Arm, RISC-V, and custom accelerators to coexist on a single compute silicon.

  • CHI-AXI bridge (CHI master ↔ AXI slave)
  • CHI-CPI bridge (cross-socket CHI)
  • AXI4-SFI bridge (Arm Scalable Fabric Interface)
  • Configurable data widths and ID widths
  • All bridges validated against SigIP NoC IP
SigIP · UCIe / D2D

UCIe D2D interface (partner)

The chip-to-chip interface that connects the Compute chiplet to the IO chiplet over UCIe. The UCIe D2D gateway (partner) with UCIe D2D interface is a SignatureIP block, meaning you get a single vendor for the full D2D link from both sides.

  • UCIe standard-compliant adapter
  • UCIe chip-to-chip interface
  • Configurable channel width and speed
  • End-to-end from Compute to IO chiplet
  • Minimal latency short-reach D2D link
  • Validated UCIe D2D interface (partner) on IO chiplet too
⚡

Strategic gap: RISC-V core partnership

SignatureIP provides all fabric, cache, and interface IP for the Compute chiplet. The CPU/RISC-V processor core itself requires a partnership (leading RISC-V core partners). SigIP has validated integrations with both, completing the full silicon stack. This is a deliberate, clean-boundary partnership model rather than a gap.

Integration flow

From topology to
taped-out silicon.

01

Define NoC requirements in iNoCulator

Configure masters, slaves, memory map, coherent groups, and QoS targets in our browser-based design interface.

02

Generate & Simulate

iNoCulator generates complete cNoC and ncNoC SystemC models for instant virtual prototyping. Validate cycle-approximate latency and bandwidth matrices.

03

Questa Sign-Off Verification

Export production-ready, synthesizable SystemVerilog RTL. Compile and verify in Siemens Questa with pre-configured UVM testbenches and VIP suites.

04

Physical Implementation

Standard cell synthesis and place & route using industry-standard tools. Static timing analysis targets 1 GHz+ operation on standard foundry process nodes.

TOOL COVERAGE

iNoCulator™ web tool generates NoC RTL directly from architectural exploration; no other EDA tool covers this step. SystemC, QEMU, and Questa flows take you from RTL to sign-off without leaving the SigIP ecosystem.

Launch iNoCulator →
UCIe Link Spec

High-bandwidth,
short-reach D2D.

The short-reach die-to-die (D2D) link provides low latency and massive parallel throughput, connecting Compute dies directly to Adjacent IO dies with minimal silicon footprint.

D2D Link parameters

Physical standardUCIe 1.1 / 2.0 compliant
Interconnect protocolFDI/RDI to CHI Rev E.b bridge
Bandwidth classUp to 32 Gbps/lane
Latency classSub-nanosecond per hop
SigIP coverageBoth sides: Compute and IO silicon
Sign-offSiemens Questa · emulation-ready
Use cases

Where the Compute
chiplet fits.

01
AI/ML accelerator SoC
UCIe D2D fabric ties RISC-V control cores, ML accelerator arrays, and HBM controllers into a coherent compute plane. SLC reduces off-chip bandwidth.
02
Chiplet disaggregation
Separate the compute silicon from IO and transport: mix process nodes, reuse the compute tile across multiple SoC variants, with UCIe as the clean boundary.
03
RISC-V server SoC
Multi-core RISC-V cluster with CHI coherency, IOMMU, and full cache hierarchy. SigIP + leading RISC-V core partners validated integration path.
04
Edge AI inference
Power-optimized NoC topology from iNoCulator balances throughput and efficiency for edge inference workloads: configurable for area-constrained designs.
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