Silicon 03 · Memory Expander
CXL 3.0 Type 3 device

Disaggregated memory
for AI and HPC.

The Memory Expander silicon delivers CXL 3.0 Type 3 endpoint capability using SignatureIP's CXL 3.2 Subsystem in CXL.mem mode. Connect DRAM capacity directly to AI accelerators and HPC nodes over CXL, without host CPU involvement in every memory transaction.

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CXL 3.0
Type 3 endpoint mode · CXL.mem
32 GT/s
PCIe Gen 6 physical layer · non-flit mode
HDM
Host-managed Device Memory decoder built in
MEMORY EXPANDER SILICONCXL 3.0 Type 3 · CXL.mem endpointCXL 3.2 SubsystemType 3 endpoint · CXL.mem · HDM decoder · SigIPCXL ControllerCXL.mem modeType 3 endpointHDM DecoderHost-managedDevice MemoryATC + ATS + DTIAddress translationpre-integratedncNoC local fabric · SigIPConfiguration and management interconnectDRAM Memory ControllerPartner-provided · DDR5 · LPDDR5 · HBM3DDR5 chDDR5 chLPDDR5HBM3 (opt)SerDes / PHYPartner-provided · PCIe Gen 6 physical layer · 32 GT/sSysWare · SigIPeFUSE · PVT sensor · Debug · AXI4-APB3UCIe D2D interface (optional)Partner-provided · for multi-silicon package integrationCXL.mem → host CPU / AI acceleratorDRAMDRAMDRAMDRAMSigIP blocksPartner-provided
CXL device types

Why Type 3 — and
why it matters for memory.

CXL defines three device types. Each targets a different role. SignatureIP's Memory Expander silicon implements Type 3 — the mode designed specifically for memory expansion and pooling.

Type 1
Accelerator without memory
Uses CXL.cache to maintain coherency with host CPU caches. No local memory. Target: smart NICs, FPGAs, DPUs that need to access host memory coherently.
Type 2
Accelerator with local memory
Uses both CXL.cache and CXL.mem. Has its own DRAM that the host CPU can also access. Target: GPUs and AI accelerators with attached HBM that want bidirectional coherent access.
Type 3 — SignatureIP
Memory expander
Uses CXL.mem only. No compute engine on the device. Presents DRAM capacity to the host as Host-managed Device Memory (HDM). The host CPU or AI accelerator maps and manages it directly. Enables memory pooling, disaggregation, and capacity beyond what fits on the CPU package. This is what the SignatureIP Memory Expander silicon implements.
IP block breakdown

What goes into the
Memory Expander silicon.

SigIP

CXL 3.2 Subsystem (Type 3 mode)

CXL.mem · HDM decoder · ATC · ATS · DTI · pre-integrated

The same CXL 3.2 Subsystem that powers the IO silicon, configured as a Type 3 CXL.mem endpoint. ATC, ATS, and DTI are pre-integrated — no separate address translation IP required. The HDM decoder exposes device DRAM to the host as Host-managed Device Memory.

  • CXL 3.0 / 3.2 Type 3 endpoint
  • CXL.mem protocol only
  • HDM decoder built in
  • ATC + ATS + DTI pre-integrated
  • Back-invalidation support (CXL 3.x)
  • Memory interleaving across channels
  • PCI-SIG certified physical layer
SigIP

ncNoC local fabric

Management interconnect · APB3 · configurable

Non-coherent NoC providing the internal management interconnect between the CXL controller, memory controller, and SysWare blocks. Generated by iNoCulator from the bandwidth and latency profile of the management plane.

  • iNoCulator-generated RTL
  • AXI4 and APB3 interfaces
  • Low-power management fabric
  • Configurable topology
SigIP

SysWare

eFUSE · PVT sensor · Debug · AXI4-APB3

Device management, security provisioning, and thermal monitoring. eFUSE for device identity and key storage. PVT sensor for thermal management of DRAM and controller. Debug interface for bring-up and production test.

  • eFUSE OTP controller
  • PVT sensor interface
  • Debug interface (JTAG)
  • AXI4-to-APB3 bridge
Partner

DRAM Memory Controller

DDR5 · LPDDR5 · HBM3 · partner-provided

The memory controller connects the CXL subsystem to physical DRAM. DDR5 is the standard choice for large-capacity pooling. LPDDR5 for power-optimised deployments. HBM3 for maximum bandwidth in AI accelerator memory expanders. Partner-provided and integrated alongside the SigIP blocks.

  • DDR5 — high capacity, server memory
  • LPDDR5 — low power, edge deployments
  • HBM3 — maximum bandwidth, AI workloads
  • ECC and RAS features
Partner

SerDes / PHY

PCIe Gen 6 physical layer · 32 GT/s · partner-provided

PCIe Gen 6 physical layer providing the CXL link to the host. The same partner SerDes used across all three silicon units in the SignatureIP platform. 32 GT/s non-flit mode, compliant with the CXL physical layer specification.

  • PCIe Gen 6 · 32 GT/s non-flit
  • x8 and x16 link widths
  • CXL-compliant equalization
Partner (optional)

UCIe D2D interface

For multi-silicon package integration · optional

When the Memory Expander silicon is packaged alongside the Compute and IO silicon in a multi-die package rather than as a standalone device, the UCIe D2D interface provides the chip-to-chip link. Partner-provided, consistent with the IO and Compute silicon.

  • UCIe standard compliant
  • Used in multi-silicon package mode only
  • Partner-provided on all silicon boundaries
Use cases

Where CXL memory
expansion fits.

01
AI inference memory pooling
Large language models need more memory than fits on the accelerator package. CXL Type 3 memory expanders add DDR5 or HBM3 capacity accessible directly by the AI accelerator over CXL.mem, without CPU involvement in data movement. Reduces model loading latency and enables larger batch sizes.
02
HPC memory disaggregation
HPC workloads with variable memory footprints benefit from disaggregated memory: nodes share a common CXL memory pool rather than each provisioning peak capacity locally. The Memory Expander silicon enables rack-scale memory pools that individual compute nodes attach to on demand.
03
Smart memory device
CXL Type 3 devices with on-chip compute can offload near-memory operations. The SignatureIP Memory Expander silicon provides the CXL.mem endpoint and memory controller integration — a starting point for smart memory device designs that add custom processing logic alongside the DRAM.
Specifications

Memory Expander silicon
key parameters.

ParameterValue
CXL versionCXL 3.0 / 3.2
CXL device typeType 3 — CXL.mem endpoint
ProtocolsCXL.mem (CXL.io for enumeration and management)
HDM decoderHost-managed Device Memory — built into CXL 3.2 Subsystem
Physical layerPCIe Gen 6 · 32 GT/s · non-flit mode
Link widthsx8 · x16
CXL IP sourceSignatureIP CXL 3.2 Subsystem (same block as IO silicon)
Memory interfacesDDR5 · LPDDR5 · HBM3 (partner memory controller)
Management fabricSignatureIP ncNoC — iNoCulator-generated RTL
SysWareeFUSE · PVT sensor · Debug · AXI4-APB3 bridge — SignatureIP
Back-invalidationSupported (CXL 3.x)
Memory interleavingAcross DRAM channels — configurable
Design verificationSiemens Questa RTL sign-off
ConsortiumCXL Consortium member
UCIe (optional)Partner-provided for multi-silicon package integration
System context

The Memory Expander silicon
in the full platform.

The Memory Expander silicon completes the three-silicon SignatureIP platform. Compute handles processing. IO handles host connectivity. Memory handles capacity — adding CXL-attached DRAM that AI accelerators and HPC nodes access directly.

COMPUTERISC-V / CPUcNoC · ncNoCIOMMU · SLCIOPCIe Gen 6CXL 3.2 SubsystemSerDes / PHYMEMORY EXPANDERCXL 3.0 Type 3CXL.mem · HDM decoderDDR5 / HBM3 (partner)UCIeCXLHost CPUAI acceleratorMore DRAM banksSignatureIP three-silicon platform · Compute · IO · Memory Expander
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Build your Memory
Expander silicon.

CXL 3.0 Type 3 silicon engagement using SignatureIP's pre-verified CXL 3.2 Subsystem. Bring your memory interface requirement and target process node — we scope the rest.

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