Lowest-power
PCIe & CXL
silicon.
PCIe Gen 6, CXL 3.2, SerDes (partner), and the UCIe D2D interface (partner): the complete IO subsystem for your chiplet. PCI-SIG certified. Designed without legacy overhead, at 1 GHz.
PCIe Gen 6 and CXL 3.2 —
designed from scratch.
No legacy architecture. No heritage PCIe Gen 3 foundations. SignatureIP's PCIe Gen 6 and CXL 3.2 controllers were designed from scratch: resulting in the lowest-power, highest-performance implementations available from any IP vendor.
PCIe Gen 6 controller
Industry-first clean-sheet PCIe Gen 6 IP: certified by PCI-SIG in September 2025. Supports all link widths at the high bandwidth efficiency with modular power management architecture.
- RC / EP dual mode: single IP, configurable at synthesis
- All link widths: x1, x2, x4, x8, x16
- 1 GHz operating frequency target
- PAM4 signaling with FLIT mode support
- TLP processing, flow control, error handling
- SFI / AXI4 / CPI / CHI host interfaces
- Advanced power management: L0s, L1, L1ss, L2
- PCI-SIG certified (32 GT/s, non-flit mode) (Sept 2025)
CXL 3.2 controller
CXL 3.2 solution with memory pooling and back-invalidation supporting memory expansion, memory pooling, and coherent device attachment: built on the same clean PCIe Gen 6 foundation, sharing partner-provided SerDes/PHY layers for area efficiency.
- CXL.io: PCIe-compatible device enumeration
- CXL.cache: device-to-host cache coherency
- CXL.mem: coherent memory access protocol
- Type 1, Type 2, and Type 3 device support
- Multi-level memory pooling and switching
- Back-invalidation support (CXL 3.x)
- CXL Consortium member: active spec contributor
SerDes / PHY (partner)
High-speed serializer/deserializer for PCIe Gen 6 and CXL 3.2 physical layer: multi-rate, PMA integration, validated across leading process nodes.
- Multi-rate: 2.5 GT/s through 32 GT/s non-flit mode
- PAM4 support for Gen 6 speeds
- PMA integration with equalization
- Process-node portable (TSMC, Samsung, Intel Foundry)
- Shared across PCIe and CXL lanes
UCIe D2D interface (partner)
The IO chiplet sits in the middle of the UCIe chain: with one gateway connecting to the Compute chiplet and a second connecting to the Memory Expander silicon. Both gateways are SignatureIP IP, giving you single-vendor D2D coverage across the full package.
- Two UCIe D2D interface (partner) instances in IO chiplet
- Compute ↔ IO: UCIe D2D link
- IO ↔ Transport: UCIe D2D link
- UCIe standard-compliant adapter
- Sub-nanosecond short-reach chip-to-chip latency
- Validated end-to-end with Compute and Memory Expanders
CXL 3.2: the
memory fabric layer.
CXL transforms the IO chiplet from a simple PCIe host into a coherent memory fabric endpoint. Type 1, 2, and 3 device support covers accelerators, smart memory expanders, and pooled memory in data-center and AI inference clusters.
| Property | Value |
|---|---|
| Spec version | CXL 3.0 / 3.2 |
| Physical layer | PCIe Gen 6 (shared) |
| Protocols supported | CXL.io · CXL.cache · CXL.mem |
| Device types | Type 1 (accel), Type 2 (coherent accel), Type 3 (mem) |
| Memory pooling | Multi-host shared memory (CXL 3.x) |
| Back-invalidation | Supported (CXL 3.x back-invalidation snoop) |
| Consortium | CXL Consortium member |
CXL.io
PCIe-compatible discovery, configuration, and non-coherent DMA. Standard enumeration path for operating systems and hypervisors: lowest integration friction.
CXL.cache
Device-side cache coherency protocol: AI accelerators cache host memory lines, dramatically reducing redundant traffic over the link while maintaining coherency guarantees.
CXL.mem
Host-coherent memory access to attached memory expanders. Enables memory pooling and tiering architectures: critical for AI training and inference at scale where capacity exceeds on-package memory.
The IO chiplet is the
UCIe hub silicon.
The IO chiplet carries two UCIe D2D interface (partner)s: one on each side of the silicon. It is the central silicon in the three-chiplet package, bridging compute traffic from the Compute chiplet through to the Memory Expander silicon and out to chip-to-chip CXL links. All three UCIe D2D interface (partner)s across the full package are SignatureIP UCIe D2D IP.