Standalone IP.
Out of the box.
30+ pre-verified blocks across four categories. Click any IP card to see the block diagram, key specifications, and download the product brief.
Coherent NoC
The central coherent interconnect fabric for CPUs, AI accelerators, and HBM controllers. CHI Rev E.b compliant. RTL generated by iNoCulator from your PPA targets.
- CHI Rev E.b protocol
- Mesh and ring topologies
- Configurable bandwidth & QoS
- iNoCulator RTL generation
- Siemens Questa sign-off
Non-Coherent NoC
Lightweight non-coherent fabric for IO peripherals, DMA engines, and subsystem controllers. Optimised for area and power. Present in all three chiplet dies.
- AXI4 / AXI4-Lite interface
- Configurable topology
- Power-optimised design
- iNoCulator toolchain shared with UCIe D2D
IOMMU
Input/Output Memory Management Unit providing address translation, memory protection, and DMA access control for peripheral devices on the NoC.
- SMMUv3 architecture
- Two-stage S1+S2 translation
- TLB & page-table walk hardware
- CHI NoC slave port integration
System-Level Cache
Last-level shared cache reducing off-chip traffic between CPU clusters, AI accelerators, and main memory. Configurable size and associativity.
- 4 MB to 32 MB+ configurable
- NWAY set-associative
- Stash transactions for prefetch
- CHI HN-F port attachment
Proxy Cache
Maintains coherency for IO devices accessing cached memory: allows non-coherent DMA masters to participate in the CHI coherency protocol without a full cache implementation.
- IO coherency participation
- Integrates with SLC/L3
- CHI RN-I interface
Protocol Bridges
Integration glue connecting heterogeneous IP blocks across different bus protocols. Enables Arm, RISC-V, and custom accelerators to coexist on one silicon.
- AXI2CHI bridge
- CHI-AXI bridge
- CHI-CPI bridge
- AXI4-SFI bridge
PCIe Gen 6 Subsystem
PCIe Gen 6 Controller operating at 32 GT/s in non-flit mode. ATC, ATS, and DTI pre-integrated: no separate address translation IP required. PCI-SIG certified.
- ATC + ATS + DTI built in
- PCI-SIG certified at 32 GT/s
- RC / EP dual mode
- All link widths x1–x16
- Power mgmt L0s · L1 · L1ss · L2
CXL 3.2 Subsystem
CXL 3.2 solution with memory pooling and back-invalidation. Shared ATC/ATS/DTI architecture with PCIe Gen 6: one NoC attachment point for both protocols.
- CXL.io · CXL.cache · CXL.mem
- Shared DTI with PCIe subsystem
- Type 1 / 2 / 3 device support
- Multi-host memory pooling (CXL 3.x)
- CXL Consortium member
UCIe D2D interface (partner)
Silicon-to-silicon interface binding all three chiplet units. UCIe D2D interface on a UCIe-standard adapter. Partner-provided on Compute, IO, and Transport silicon.
- UCIe standard compliant
- Partner-provided on boundaries
- UCIe D2D interface
- Sub-nanosecond D2D latency
Ethernet MAC
High-efficiency Ethernet MAC controller with low latency processing. Supports standard industrial interfaces and integrates easily with DMA.
- 10 / 100 / 1000 Mbps speeds
- RGMII and MII interfaces
- Descriptor-based DMA ring
- Configurable FIFO depth
DMA Engine
Multi-channel Direct Memory Access engine for high-throughput data movement between memory and IO peripherals, reducing CPU overhead.
- Multi-channel DMA
- AXI4 master interface
- Scatter-gather support
- APB3 configuration interface
Boot Flash Controller
SPI NOR flash controller with integrated DMA for fast secure boot image loading. Supports XIP (execute-in-place) and secure boot paths.
- Integrated DMA engine
- XIP execute-in-place
- Secure boot path
- APB3 configuration
eFUSE Controller
One-time programmable eFUSE interface for device identity, security key provisioning, and configuration lock. APB3 register interface.
- OTP read / program
- APB3 interface
- Security key storage
- Redundancy / ECC
PVT Sensor Interface
Interface controller for on-chip Process/Voltage/Temperature sensors. Enables thermal management and process corner detection.
- P / V / T monitoring
- APB3 register interface
- Interrupt on threshold
- All silicon compatible
AXI4-to-APB3 Bridge
High-to-low speed bridge connecting AXI4 CPU fabric to APB3 control plane, enabling CPU access to all configuration registers.
- AXI4 slave → APB3 master
- Optional clock domain crossing
- Configurable address map
Debug Interface
Debug and trace interface controller supporting JTAG and SWD protocols for CPU and system-level debug, including CoreSight integration.
- JTAG + SWD
- CoreSight compatible
- APB3 interface
SPI Master + Slave
SPI master controller with 4 configurable chip selects for external peripherals. Separate SPI slave for host-commanded configuration.
- Master: 4 chip selects
- All SPI modes 0–3
- APB3 config interface
- Multi-use per design
I2C Master + Slave
I2C master controller for power management ICs, sensors, and EEPROMs. Four instances in the Pioneer reference design.
- 100 kHz / 400 kHz / 1 MHz
- Multi-master arbitration
- ×4 instances in Pioneer
- Multi-use per design
UART
Universal Asynchronous Receiver/Transmitter for console output, debug logging, and host communication with FIFO buffering.
- Configurable baud rate
- TX/RX FIFO
- APB3 interface
- Multi-use per design
Watchdog Timer
Hardware watchdog timer generating system reset or interrupt on counter expiry. Present across all three chiplet dies.
- Configurable timeout
- Reset or interrupt output
- Present on all three silicon units
- Multi-use per design
General-Purpose Timers
Configurable general-purpose timer block supporting PWM generation, input capture, and compare modes for system timing.
- PWM generation
- Input capture / output compare
- APB3 interface
- Multi-use per design
GPIO Controller
General-purpose IO controller with configurable pin count, direction control, and interrupt-on-change support.
- Configurable bit width
- Interrupt-on-change
- APB3 register access
- Multi-use per design