Founded to fix NoC design.
Built into a silicon platform.
SignatureIP was founded with one conviction: the NoC backbone of every SoC was too hard to design, too slow to configure, and too locked up in legacy vendor architectures. Today we are a full silicon infrastructure IP platform, delivering pre-verified PCIe Gen 6, CXL 3.2, and NoC IP alongside custom Compute Subsystem and IO Subsystem chiplet design engagements.
The team
Leadership spanning silicon architecture, engineering, operations, finance, and people: building IP that SoC teams actually want to use.
Purna built and exited semiconductor teams at Adaptec, Broadcom, Semtech, and NXP before co-founding Marquee Semiconductor and then SignatureIP. He holds five US patents in SoC design and verification. At SignatureIP he set the technical direction: clean-sheet IP with no legacy overhead, tooling that generates RTL from PPA targets, and an engagement model that works for lean fabless teams. BSEE, NIT Rourkela; MSEE, University of Toledo.
Ramana leads SignatureIP's IP technology vision. He architected the coherent and non-coherent NoC families and drives the CXL 3.2 and PCIe Gen 6 subsystem roadmap. Previously he held senior silicon roles at Indie Semiconductor, Eximius Design, and RED Digital Cinema.
Michael runs SignatureIP's global engineering delivery across embedded systems and intelligent platforms. He has shipped multiple commercially successful products and holds international patents in image processing. Double degree in Physics and Computer Engineering, Ateneo de Manila.
Ewald leads strategic growth at SignatureIP. He spent 30 years running P&L-responsible semiconductor and automotive organisations as Managing Director, VP, and GM, with deep domain expertise in SoCs, functional safety, and AI platforms for mobility.
Suchitra owns program execution and process governance at SignatureIP. Over 30 years she has run large-scale engineering programs in both public and private sectors and built the operational infrastructure that keeps multi-country delivery on schedule. BE Electronics, BITS Pilani.
Reyann leads technical pre-sales at SignatureIP: qualifying opportunities, running architecture reviews with prospective customers, and matching the right IP blocks to each SoC design. He brings 13 years of RTL design and verification experience from Canon Japan, Canon Philippines, and Marquee Semiconductor. BS Electronics Engineering, De La Salle University.
Fides leads software engineering at SignatureIP across AI/ML, telecom, and SoC platform layers. He has delivered production systems for Nokia, AI-Wave Computing, and Cambria Software, and is a recipient of the Presidential Award for Science and Technology. BS Computer Engineering, PUP.
Niranjan has spent 35 years in technology and research, including roles at Fujitsu, NASA's Space Station Program, and the Bhabha Atomic Research Center. At SignatureIP he owns talent, culture, and organizational development. MSc Computer Science, UK; Physics, Utkal University.
Hara oversees finance, tax structuring, and ASEAN and North Asia expansion at SignatureIP. Since 2019 he has built government and trade body partnerships across the region. Previously with Sodexo, SSP, Minor Food Group, and Wine Connections. Chartered Accountant, ICAI and CPA Australia.
Four countries, one delivery model
SignatureIP's engineering and operations span the US, India, Singapore, the Philippines, and the MarqueeSemi partner network. Silicon Valley architecture leadership coordinates with deep engineering execution across time zones.
In India, SignatureIP actively develops the semiconductor ecosystem in Bhubaneswar, Odisha, building local engineering capability alongside delivering IP and chiplet projects for global customers.
Marquee Semiconductor extends SignatureIP's engineering capacity for chiplet design engagements, providing additional ASIC design, verification, and integration capability across multiple geographies. Validated integration paths with a leading RISC-V core partner.
Where we've come from,
where to find us next
Book a meeting at any show
Live iNoCulator demo, PCIe/CXL subsystem briefing, or a chiplet design conversation at the booth: tell us which show and we'll confirm a time.
Contact us to scheduleStandards, partners, certifications
Standards bodies
Active membership in the protocol standards that define silicon infrastructure IP.
Technology partners
Validated integrations with leading EDA, processor, and ecosystem partners.
Design services partner
Marquee Semiconductor extends SignatureIP's engineering capacity for custom chiplet design engagements.
Get in touch
Headquarters
Milpitas, CA 95035
United States
Ready to work with the SignatureIP team?
License standalone IP, commission a chiplet design, or start a technical conversation. We respond within one business day.